(a) Field of the Invention
The present invention relates to an output buffer circuit having a variable output impedance, and more particularly, to an improvement of such an output buffer circuit to obtain a higher speed with a reduced circuit scale.
(b) Description of the Related Art
In general, it is desired for an output buffer circuit to adapt to a low amplitude signal along with a higher speed of signal transmission. In order for the adaptation, it is necessary to remove or reduce the reflection of the transmitted data signal along the signal transmission line. The removal of the reflection is generally achieved by an impedance matching between the output impedance of the output buffer circuit and the impedance of the signal transmission line connected thereto. The impedance matching can be obtained by an output circuit having a variable output impedance.
FIG. 1 is shows a conventional output buffer circuit having a variable output impedance. The buffer circuit includes an impedance control terminal 21, a pull-up section 26 including parallel nMOS transistors 27 to 29, a comparator 15, UP/DOWN counter 16, a NOR gate array 30 including NOR gates 31 to 33, and an output section 34 including parallel nMOS transistors 35 to 37.
The impedance control terminal 21 is connected to the source line Vcc via the pull-up section 26 and to the ground via an external resistor 14 provided outside the chip of the semiconductor device having the output buffer circuit. The comparator 15 compares the potential of the impedance control terminal 21 against a voltage level of Vcc/2 to deliver a high level or a low level to the UP/DOWN counter 16 based on the result of the comparison. The UP/DOWN counter 16 receives a count clock signal 103 through a clock input terminal 23 and up-counts the clock pulses of the count clock signal if the potential of the impedance control terminal 21 is lower than Vcc/2, and down-counts if the potential of the impedance control terminal 21 is higher than Vcc/2.
The coded outputs 104 to 106 of the UP/DOWN counter 16 are delivered to the respective gates of nMOS transistors 27 to 29 in the pull-up section 26 and to respective first inputs of NOR gates 31 to 33 in the NOR gate array 30. If the potential of the impedance control terminal 21 is lower than Vcc/2, the potential of the impedance control terminal 21 is raised by nMOS transistors 27 to 29 in the pull-up section 26 by increasing the ON-current thereof, whereas if the potential of the impedance control terminal 21 is higher than Vcc/2, the potential of the impedance control terminal 21 is lowered by nMOS transistors 27 to 29. After iterated control, nMOS transistors 27 to 29 in the pull-up section 26 enters into a stable state wherein the overall resistance of nMOS transistors 27 to 29 is substantially equal to the resistance of the external resistor 14. Thus, the impedance control terminal 21 stays substantially at Vcc/2, while being subjected to a slight UP/DOWN control by 1 bit of the coded outputs 104 to 106.
On the other hand, the coded outputs 104 to 106 supplied to the respective first inputs of NOR gates 31 to 33 in the NOR gate array 30 are NORed with a data signal 108 supplied through a data input terminal 14 to the respective second inputs of NOR gates 31 to 33. The NORed data are supplied to respective gates of nMOS transistors 35 to 37 in the output section 34, and control the ON-resistances of nMOS transistors 35 to 37 in the output section 36 similarly to the ON-resistances of nMOS transistors 27 to 29 in the pull-up section 26. After the pull-up section 26 enters into the stable state, so long as the data signal 108 supplied through the data input terminal 24 is at a L-level, the output impedance at the output terminal 25 of the output buffer circuit is determined by the overall ON-resistance of nMOS transistors 35 to 37, which is determined by the overall ON-resistance of transistors 25 to 27 and the ratio of the overall transistor size of nMOS transistors 27 to 29 to the overall transistor size of nMOS transistors 37 to 39. Thus, it is possible to control the output impedance at the output terminal 25 based on resistance of the external resistor 14 during transmission of a high level signal. The resistance of the external resistor 14 can be selected at any value from outside to remove the signal reflection.
In the conventional output buffer circuit, the data input terminal 24 for receiving the data signal 108 has a large parasitic capacitance because of the plurality of NOR gates 31 to 33 connected to the data input terminal 24, which impedes a high speed signal transmission.
In addition, the number of nMOS transistors 27 to 29 in the pull-up section 26 and the number of nMOS transistors 35 to 37 in the output section 34 are large, which raise the circuit scale of the output buffer circuit.